Active R&D Engineer — Available for Senior Opportunities

Abanoub AbdelMessieh

Embedded Firmware Engineer focused on deterministic RTOS, audio DSP, and secure resource constrained systems

Turin, Italy — Open to Relocation Within EU

Professional Experience

Urmet S.p.A.

Nov 2022 — Present

Embedded Software Designer (Headquarters in Turin)

Driving firmware innovation within the Technology Innovation division for next-generation IP-based and 2-wire smart door entry and building automation systems. Focused on porting complex network stacks to resource-constrained bare-metal silicon and establishing reproducible modern compilation pipelines.

  • Ported and stripped a custom bare-metal version of the POSIX-based Baresip client to STM32 and NationsTech (N32) ARM Cortex-M4 microcontrollers, enabling seamless SIP/SDP signaling with Linux-based counterparts.
  • Architected and developed a 32KB Layer 2 secure FOTA bootloader utilizing micro-ecc (uECC) for EC-PKI authentication, completely bypassing IP/UDP stacks to operate over raw MAC addresses.
  • Designed and containerized the R&D build environment using Docker, streamlining compilation workflows for N32 and STM32 applications via ARM CMSIS toolbox.
  • Optimized real-time G.722 audio processing routines in Cortex-M4 assembly, reducing loop execution from 4ms to 3ms to guarantee low-jitter streams vital for remote Acoustic Echo Cancellation stability.
  • Refactored Microchip 10BASE-T1S MACPHY OPEN Alliance TC6 drivers to operate asynchronously via SPI DMA complete interrupts, eliminating polling overhead and slashing ping latency by 1ms.
  • Interfaced bare-metal nodes with Allwinner V853s Linux SoCs, user-space testing servers in Go and compiling custom Rust DeepFilterNet plugins for high-performance Edge AI active noise cancellation.

Adgenera (Curricular Internship)

Sep 2022 — Oct 2022

Industrial Automation Intern

Contributed to the real-time baggage handling system renewal project at Zürich Airport, configuring high-reliability industrial PLC control nodes.

  • Configured Siemens SIMATIC S7-1500 controllers in Structured Control Language (SCL) over TIA Portal v17.
  • Participated in automated simulation testing tracking edge-case behaviors under peak baggage sorting throughput scenarios.

Featured Projects

Professional architectures (proprietary code restricted) & academic research codebases.

Professional / R&D Sandbox

ARM Cortex-M4 Secure FOTA & Networking Sandbox

PROPRIETARY

A high-fidelity, heterogeneous R&D simulation environment running FreeRTOS, FreeRTOS+TCP, coreMQTT, and PSA Crypto to validate secure, standard-compliant FOTA updates.

The Engineering Challenge

Validating secure, multi-node FOTA updates on physical hardware (like STM32) is slow, hard to automate, and makes regression testing difficult. Standard mTLS and MQTT libraries consume significant heap memory and require careful optimization on constrained MCUs.

Solution & Architecture

Architected a dual-platform local emulation sandbox with a QEMU-emulated Cortex-M4 board running the official FreeRTOS OTA Agent and a virtual TAP bridge. Integrated TLS 1.3-only Mutual TLS (mTLS) over Mosquitto using MbedTLS/PSA Crypto. Developed an asyncio-based AWS Jobs emulator to stream binary CBOR-encoded firmware blocks. Managed the entire cross-compilation environment using a reproducible Nix Flake.

FreeRTOS FreeRTOS+TCP coreMQTT MbedTLS PSA Crypto TLS 1.3 mTLS (ECDSA) QEMU (mps2-an386) STM32 Nucleo CBOR AWS IoT Jobs CMake Ninja Nix Flakes C
flake.nix
nix
{
  description = "FreeRTOS MQTT Sandbox & NUCLEO-C5A3ZG Build Environment";

  inputs = {
    nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
    flake-utils.url = "github:numtide/flake-utils";
  };

  outputs = { self, nixpkgs, flake-utils }:
    flake-utils.lib.eachDefaultSystem (system:
      let
        pkgs = import nixpkgs { inherit system; };
      in
      {
        devShells.default = pkgs.mkShell {
          buildInputs = with pkgs; [
            # Build Tools
            gnumake
            cmake
            ninja
            
            # Cross-Compilation Toolchain
            gcc-arm-embedded
            
            # Debugging & Flashing
            openocd
            gdb
            
            # Host Emulation & Broker
            qemu
            mosquitto
            
            # Scripting
            python3
            python3Packages.pip
            python3Packages.virtualenv

            # Host Libraries for Cortex-A7 Linux Device Agent Proxy
            openssl
            paho-mqtt-c
            pkg-config
          ];

          shellHook = ''
            echo "========================================================"
            echo "🚀 Nix Environment Active: FreeRTOS Sandbox"
            echo "   Toolchain: $(arm-none-eabi-gcc --version | head -n1)"
            echo "   CMake    : $(cmake --version | head -n1)"
            echo "========================================================"
          '';
        };
      }
    );
}
> TLS 1.3 mTLS FOTA Handshake Loop SYSTEM_ARCHITECTURE
Local AWS FOTA Emulator (Python) Cortex-M4 Guest (FreeRTOS)
Publishes AWS Job Doc → mTLS Broker → Subscribed to /jobs/notify-next
Decodes Bitmap Job Document ← CBOR Bitmap ← Requests binary chunk bits
Streams 256B CBOR block → mTLS/TCP 8883 → Computes SHA-256 natively via PAL
Pushes Success status ← verification ← Reboots (AIRCR) & Self-Tests
Professional / Proprietary System

High-Performance Deterministic IP Audio Engine

PROPRIETARY

A real-time, low-latency VoIP audio application utilizing FreeRTOS and LwIP on constraint-driven Cortex-M4 hardware, featuring precise audio-network synchronicity.

The Engineering Challenge

Remote Linux-based systems running full Baresip required sub-millisecond packet turnaround and consistent low-jitter streams to keep acoustic echo cancellation (AEC) models stable. Standard VoIP and network libraries exceeded the memory and timing budgets.

Solution & Architecture

Ported and stripped a custom bare-metal version of the POSIX-based Baresip client to Cortex-M4 to mimic full Linux SIP/INVITE behaviors. Optimized the G.722 codec in ASM utilizing Cortex-M4 saturating arithmetic, saving 25% CPU execution. Refactored the Microchip 10-BASE T1S OPEN Alliance TC6 driver to use SPI DMA complete interrupts instead of polling, keeping the entire duplex TX/RX stream tightly constrained to an 8ms latency budget per pipe.

Custom PCB CUBE IDE STM32 C ARM v7-E Assembly FreeRTOS LwIP SPI-DMA 10 BASE-T1S TC6 SIP RTP I2S-DMA Nuvoton CODEC Nationstech N32
>> SEGGER SYSTEMVIEW SCOPE
TIMEBASE: 1.00 ms/div
FreeRTOS G.722 Context Trace
CH_1 I2S_AUDIO_DMA
CH_2 G722_ASM_DECODE
CH_3 LwIP_IP_STACK
CH_4 TC6_SPI_DMA
Professional / Proprietary System

Secure Layer-2 Ethernet FOTA Bootloader

PROPRIETARY

An ultra-compact (32KB) secure firmware-over-the-air (FOTA) bootloader operating completely at Layer 2 without an IP or OS stack, utilizing Elliptic-Curve PKI for cryptographic validation.

The Engineering Challenge

Standard secure update clients rely on mbedTLS, X.509 certificate parsers, and full TCP/IP stacks, which easily exceed the 32KB bootloader boundary on a 256KB Flash MCU.

Solution & Architecture

Designed a lightweight custom Layer 2 TLS-like handshake that operates over raw MAC addresses, completely bypassing the ARP, IPv4/IPv6, and UDP stacks in the bootloader. Integrated micro-ecc (uECC) to perform EC-PKI signature verification of incoming firmware chunks. Wrote raw Ethernet drivers directly interfacing with the LAN8651 10BASE-T1S MACPHY via raw SPI commands, enabling secure, low-overhead firmware upgrades directly to the internal flash blocks.

C Bare-Metal TLS uECC PKI 10BASE-T1S L2-Networking FOTA Secure Boot
> Layer 2 Cryptographic Bootloader Handshake SYSTEM_ARCHITECTURE
L2 Provisioning Server (Go) Bootloader (32KB Bare-Metal)
Sends Raw MAC Frame → Broadcast → Listens on raw MAC port
Verify Session Challenge ← Handshake (ECDH) ← Generates ECDH Session Key
Encrypts Chunk (AES) → Payload → Decrypts in-place (no IP heap)
Acks Chunk ← verification ← uECC Image Check & Flash
Academic / Master's (Politecnico di Torino - Italy)

Deterministic Time-Triggered FreeRTOS Fork

PROPRIETARY

A customized fork of the FreeRTOS Kernel v11.2.0 implementing a deterministic, time-triggered timeline-based scheduling scheme for safety-critical systems on ARM Cortex-M3.

The Engineering Challenge

The default event-driven priority-based scheduler in FreeRTOS exhibits timing jitter and lacks temporal isolation, making it non-compliant with strict safety standards (like ASIL-C/IEC 61508).

Solution & Architecture

Modified the scheduler core (tasks.c) to select tasks based on a static offline timeline of Major/Minor frames mapped directly to the system tick. Integrated hard-deadline violation hooks for safe, ISR-safe task termination, validated under QEMU.

Compliance Patterns & Features

  • Subframe assignment: Tasks are rigidly bound to specific minor frames with absolute deadlines.
  • Clock-synchronous determinism: Achieved zero jitter, with activation bounded to 1 tick.

QEMU Real-Time Verification

Test Scenario Status Analysis / Findings
Normal Execution PASSED Perfect timeline adherence, 0 violations.
HRT Overrun PASSED Safety hooks trigger immediate, ISR-safe task kills.
C RTOS Internals QEMU Time-Triggered Architecture Safety-Critical Design
portable/kernel/timelinescheduler.h
c
/*
 * FreeRTOS Kernel V11.2.0
 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
 * the Software without restriction, including without limitation the rights to
 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
 * the Software, and to permit persons to whom the Software is furnished to do so,
 * subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * https://www.FreeRTOS.org
 * https://github.com/FreeRTOS
 *
 */

#ifndef INC_TIMELINE_SCHEDULER_H
#define INC_TIMELINE_SCHEDULER_H

#ifndef INC_FREERTOS_H
    #error "include FreeRTOS.h must appear in source files before include timelinescheduler.h"
#endif

/**
 * @brief Defines the classification of tasks within the timeline scheduler.
 *
 * The scheduler distinguishes between tasks that require strict deterministic
 * timing guarantees (Hard Real-Time) and those that run on a best-effort basis
 * during idle periods (Soft Real-Time).
 */
typedef enum
{
    /* Tasks that must execute within a specific subframe window and strictly
     * adhere to start and end times. */
    TASK_HARD_RT = 0,

    /* Tasks that execute in the remaining time of a subframe after Hard Real-Time
     * tasks have completed. They are scheduled in a fixed order. */
    TASK_SOFT_RT = 1
} TaskType_t;

/**
 * @brief Configuration structure for a single task in the timeline.
 *
 * This structure defines all properties required by the scheduler to manage
 * the task's execution, including its timing constraints, stack requirements,
 * and category.
 */
typedef struct
{
    /* A descriptive name for the task. This is used primarily for debugging
     * and identification purposes. */
    const char * pcTaskName;

    /* Pointer to the function that implements the task. The task function must
     * follow the standard FreeRTOS task signature: void vTaskCode( void * pvParameters ); */
    TaskFunction_t pxTaskCode;

    /* The category of the task (Hard Real-Time or Soft Real-Time). */
    TaskType_t xType;

    /* For Hard Real-Time tasks: The offset in ticks from the start of the
     * assigned subframe at which the task must begin execution.
     * For Soft Real-Time tasks: This field is ignored. */
    TickType_t xStartTime;

    /* For Hard Real-Time tasks: The deadline in ticks relative to the start
     * of the assigned subframe. The task must complete execution before this time.
     * For Soft Real-Time tasks: This field is ignored. */
    TickType_t xEndTime;

    /* The index of the subframe (0 to configTIMELINE_SUBFRAMES_PER_CYCLE - 1) in which this task is
     * scheduled to run. This is only relevant for Hard Real-Time tasks. */
    uint32_t ulSubframeId;

    /* The number of words (not bytes) to allocate for the task's stack. For example,
     * if the stack is 32-bits wide, a value of 100 allocates 400 bytes. */
    uint16_t usStackDepth;
} TimelineTaskConfig_t;

/**
 * @brief Initializes the timeline scheduler with the provided task configuration.
 *
 * This function parses the configuration array, creates the necessary internal
 * structures, and prepares the tasks for execution. It must be called before
 * the FreeRTOS scheduler is started via vTaskStartScheduler().
 *
 * @note The global configuration parameters configTIMELINE_TASK_COUNT, configTIMELINE_MAJOR_FRAME_TICKS, and configTIMELINE_MINOR_FRAME_TICKS
 *       must be defined in FreeRTOSConfig.h.
 *
 * @param[in] cfg Pointer to an array of TimelineTaskConfig_t structures. The array
 *                must contain exactly configTIMELINE_TASK_COUNT entries, defining the complete
 *                schedule for the system.
 */
void vConfigureScheduler( const TimelineTaskConfig_t * cfg );

/**
 * @brief Forcefully terminates a task and reschedules it for the next major frame.
 *
 * This function is designed to be called from timeline hooks (which run in 
 * interrupt context) to enforce conditional dependencies or handle faults.
 *
 * @param[in] xTask The handle of the task to terminate.
 */
#if ( INCLUDE_vTaskTimelineTerminate == 1 )
    void vTaskTimelineTerminateFromISR( TaskHandle_t xTask );
#endif

#endif /* INC_TIMELINE_SCHEDULER_H */
Academic / Bachelor's (University of Arkansas - USA)

Versatile Embedded & Network Systems Suite

A versatile showcase of fundamental software and hardware engineering modules developed during Bachelor's studies, spanning Assembly driver programing, network sockets, and OOP.

The Engineering Challenge

To prove rigorous fundamental training in bare-metal architectures, I/O registers, low-level interrupts, socket communication, and object-oriented paradigms across diverse environments.

Solution & Architecture

Compiled a highly modular suite of academic source codes: low-level ARM/MSP assembly drivers (mapping I/O ports, registers, PWM, and ISR vectors) built during exchange studies at the University of Arkansas, USA; clean client-server socket engines in C; and application-level object-oriented systems (like a complete vaccination campaign tool in Java).

Assembly C Java Microcontrollers I/O Registers Socket Programming OOP
>> MSP430 SILICON PROTOTYPE
Politecnico di Torino Silicon Prototyping
CH_1 TARGET: MSP430
CH_2 PERIPHERAL: GPIO/TIMERS
CH_3 BUILT: POLITO LABS
CH_4 STATUS: VERIFIED

Engineering Capabilities

A transparent, impact-focused assessment of my strengths, R&D skills, and daily workflows.

> Core Expertise

Where I add immediate, production-ready value

Bare-Metal & RTOS Internals

Designing custom scheduler hooks and timeline-based task tables in FreeRTOS. Managing low-level hardware resources with strict memory and temporal boundaries.

Deterministic Audio & DSP Optimization

Developing real-time audio pipelines. Hand-optimizing expensive loops .

Interrupt-Driven Architectures

Refactoring drivers to use non-blocking structures, drastically reducing interrupt latency.

Microcontroller Bring-Up & Interfacing

Initializing low-end silicon from scratch. Interfacing robustly with higher-level Linux SoCs over low-overhead networks.

> Emerging Capabilities

Active areas of R&D and rapid development

Cryptography and hardware Security

Bypassing heavy IP/TLS stacks by constructing micro-ecc (uECC) and EC-PKI authentication handshakes directly over raw MAC addresses.

Edge AI & User-Space Integration

Compiling and integrating neural-network audio utilities (like Rust-based DeepFilterNet) into Tina Linux based targets.

> Engineering Workflow & Preferences

My toolset, environmental preferences, and R&D acceleration

Work Environment & Location

I operate best in professional English-speaking environments. Comfortable with fully remote, hybrid, or on-premises roles where engineering execution and ownership are respected.

Architectural Mapping (Pen & Paper)

Before writing a single line of code, I map out state machines, memory limits, and hardware timing on paper to ensure structural soundness.

VScode & Reproducible Builds with Nix Flakes

I lean strongly toward Nix Flakes over traditional Docker for development environments.

Deep Step-by-Step Debugging

Using Segger J-Link, Ozone, System View, and GDB for precise instruction stepping, task tracing but i still enjoy a small oscilloscope on my desk while maintaining asserts and printf debugging

Low-Overhead Meetings

I highly value efficient, action-oriented face-to-face engineering alignments. I prefer targeted discussion over passive, unproductive status meetings.

AI-Assisted Peer Programming

treating AI as a highly capable peer programmer,Gemini CLI, Claude and Codex are my personal favorites