Abanoub AbdelMessieh
Embedded Firmware Engineer focused on deterministic RTOS, audio DSP, and secure resource constrained systems
Professional Experience
Urmet S.p.A.
Nov 2022 — PresentEmbedded Software Designer (Headquarters in Turin)
Driving firmware innovation within the Technology Innovation division for next-generation IP-based and 2-wire smart door entry and building automation systems. Focused on porting complex network stacks to resource-constrained bare-metal silicon and establishing reproducible modern compilation pipelines.
- ◆ Ported and stripped a custom bare-metal version of the POSIX-based Baresip client to STM32 and NationsTech (N32) ARM Cortex-M4 microcontrollers, enabling seamless SIP/SDP signaling with Linux-based counterparts.
- ◆ Architected and developed a 32KB Layer 2 secure FOTA bootloader utilizing micro-ecc (uECC) for EC-PKI authentication, completely bypassing IP/UDP stacks to operate over raw MAC addresses.
- ◆ Designed and containerized the R&D build environment using Docker, streamlining compilation workflows for N32 and STM32 applications via ARM CMSIS toolbox.
- ◆ Optimized real-time G.722 audio processing routines in Cortex-M4 assembly, reducing loop execution from 4ms to 3ms to guarantee low-jitter streams vital for remote Acoustic Echo Cancellation stability.
- ◆ Refactored Microchip 10BASE-T1S MACPHY OPEN Alliance TC6 drivers to operate asynchronously via SPI DMA complete interrupts, eliminating polling overhead and slashing ping latency by 1ms.
- ◆ Interfaced bare-metal nodes with Allwinner V853s Linux SoCs, user-space testing servers in Go and compiling custom Rust DeepFilterNet plugins for high-performance Edge AI active noise cancellation.
Adgenera (Curricular Internship)
Sep 2022 — Oct 2022Industrial Automation Intern
Contributed to the real-time baggage handling system renewal project at Zürich Airport, configuring high-reliability industrial PLC control nodes.
- ◆ Configured Siemens SIMATIC S7-1500 controllers in Structured Control Language (SCL) over TIA Portal v17.
- ◆ Participated in automated simulation testing tracking edge-case behaviors under peak baggage sorting throughput scenarios.
Featured Projects
Professional architectures (proprietary code restricted) & academic research codebases.
ARM Cortex-M4 Secure FOTA & Networking Sandbox
A high-fidelity, heterogeneous R&D simulation environment running FreeRTOS, FreeRTOS+TCP, coreMQTT, and PSA Crypto to validate secure, standard-compliant FOTA updates.
The Engineering Challenge
Validating secure, multi-node FOTA updates on physical hardware (like STM32) is slow, hard to automate, and makes regression testing difficult. Standard mTLS and MQTT libraries consume significant heap memory and require careful optimization on constrained MCUs.
Solution & Architecture
Architected a dual-platform local emulation sandbox with a QEMU-emulated Cortex-M4 board running the official FreeRTOS OTA Agent and a virtual TAP bridge. Integrated TLS 1.3-only Mutual TLS (mTLS) over Mosquitto using MbedTLS/PSA Crypto. Developed an asyncio-based AWS Jobs emulator to stream binary CBOR-encoded firmware blocks. Managed the entire cross-compilation environment using a reproducible Nix Flake.
High-Performance Deterministic IP Audio Engine
A real-time, low-latency VoIP audio application utilizing FreeRTOS and LwIP on constraint-driven Cortex-M4 hardware, featuring precise audio-network synchronicity.
The Engineering Challenge
Remote Linux-based systems running full Baresip required sub-millisecond packet turnaround and consistent low-jitter streams to keep acoustic echo cancellation (AEC) models stable. Standard VoIP and network libraries exceeded the memory and timing budgets.
Solution & Architecture
Ported and stripped a custom bare-metal version of the POSIX-based Baresip client to Cortex-M4 to mimic full Linux SIP/INVITE behaviors. Optimized the G.722 codec in ASM utilizing Cortex-M4 saturating arithmetic, saving 25% CPU execution. Refactored the Microchip 10-BASE T1S OPEN Alliance TC6 driver to use SPI DMA complete interrupts instead of polling, keeping the entire duplex TX/RX stream tightly constrained to an 8ms latency budget per pipe.
Secure Layer-2 Ethernet FOTA Bootloader
An ultra-compact (32KB) secure firmware-over-the-air (FOTA) bootloader operating completely at Layer 2 without an IP or OS stack, utilizing Elliptic-Curve PKI for cryptographic validation.
The Engineering Challenge
Standard secure update clients rely on mbedTLS, X.509 certificate parsers, and full TCP/IP stacks, which easily exceed the 32KB bootloader boundary on a 256KB Flash MCU.
Solution & Architecture
Designed a lightweight custom Layer 2 TLS-like handshake that operates over raw MAC addresses, completely bypassing the ARP, IPv4/IPv6, and UDP stacks in the bootloader. Integrated micro-ecc (uECC) to perform EC-PKI signature verification of incoming firmware chunks. Wrote raw Ethernet drivers directly interfacing with the LAN8651 10BASE-T1S MACPHY via raw SPI commands, enabling secure, low-overhead firmware upgrades directly to the internal flash blocks.
Deterministic Time-Triggered FreeRTOS Fork
A customized fork of the FreeRTOS Kernel v11.2.0 implementing a deterministic, time-triggered timeline-based scheduling scheme for safety-critical systems on ARM Cortex-M3.
The Engineering Challenge
The default event-driven priority-based scheduler in FreeRTOS exhibits timing jitter and lacks temporal isolation, making it non-compliant with strict safety standards (like ASIL-C/IEC 61508).
Solution & Architecture
Modified the scheduler core (tasks.c) to select tasks based on a static offline timeline of Major/Minor frames mapped directly to the system tick. Integrated hard-deadline violation hooks for safe, ISR-safe task termination, validated under QEMU.
Compliance Patterns & Features
- ✔ Subframe assignment: Tasks are rigidly bound to specific minor frames with absolute deadlines.
- ✔ Clock-synchronous determinism: Achieved zero jitter, with activation bounded to 1 tick.
QEMU Real-Time Verification
| Test Scenario | Status | Analysis / Findings |
|---|---|---|
| Normal Execution | PASSED | Perfect timeline adherence, 0 violations. |
| HRT Overrun | PASSED | Safety hooks trigger immediate, ISR-safe task kills. |
A versatile showcase of fundamental software and hardware engineering modules developed during Bachelor's studies, spanning Assembly driver programing, network sockets, and OOP.
The Engineering Challenge
To prove rigorous fundamental training in bare-metal architectures, I/O registers, low-level interrupts, socket communication, and object-oriented paradigms across diverse environments.
Solution & Architecture
Compiled a highly modular suite of academic source codes: low-level ARM/MSP assembly drivers (mapping I/O ports, registers, PWM, and ISR vectors) built during exchange studies at the University of Arkansas, USA; clean client-server socket engines in C; and application-level object-oriented systems (like a complete vaccination campaign tool in Java).
Engineering Capabilities
A transparent, impact-focused assessment of my strengths, R&D skills, and daily workflows.
> Core Expertise
Where I add immediate, production-ready value
Bare-Metal & RTOS Internals
Designing custom scheduler hooks and timeline-based task tables in FreeRTOS. Managing low-level hardware resources with strict memory and temporal boundaries.
Deterministic Audio & DSP Optimization
Developing real-time audio pipelines. Hand-optimizing expensive loops .
Interrupt-Driven Architectures
Refactoring drivers to use non-blocking structures, drastically reducing interrupt latency.
Microcontroller Bring-Up & Interfacing
Initializing low-end silicon from scratch. Interfacing robustly with higher-level Linux SoCs over low-overhead networks.
> Emerging Capabilities
Active areas of R&D and rapid development
Cryptography and hardware Security
Bypassing heavy IP/TLS stacks by constructing micro-ecc (uECC) and EC-PKI authentication handshakes directly over raw MAC addresses.
Edge AI & User-Space Integration
Compiling and integrating neural-network audio utilities (like Rust-based DeepFilterNet) into Tina Linux based targets.
> Engineering Workflow & Preferences
My toolset, environmental preferences, and R&D acceleration
Work Environment & Location
I operate best in professional English-speaking environments. Comfortable with fully remote, hybrid, or on-premises roles where engineering execution and ownership are respected.
Architectural Mapping (Pen & Paper)
Before writing a single line of code, I map out state machines, memory limits, and hardware timing on paper to ensure structural soundness.
VScode & Reproducible Builds with Nix Flakes
I lean strongly toward Nix Flakes over traditional Docker for development environments.
Deep Step-by-Step Debugging
Using Segger J-Link, Ozone, System View, and GDB for precise instruction stepping, task tracing but i still enjoy a small oscilloscope on my desk while maintaining asserts and printf debugging
Low-Overhead Meetings
I highly value efficient, action-oriented face-to-face engineering alignments. I prefer targeted discussion over passive, unproductive status meetings.
AI-Assisted Peer Programming
treating AI as a highly capable peer programmer,Gemini CLI, Claude and Codex are my personal favorites